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3 ? 19 contents 1.module classification information 2.precautions in use of lcd modules 3.general specification 4.absolute maximum ratings 5.electrical characteristics 6.optical characteristics 7.interface pin function 8.contour drawing & block diagram 9.function description 10.character generator rom pattern 11.instruction table 12.timing characteristics 13.initializing of lcm 14.quality assurance 15.reliability
4 ? 19 1.module classification information w p 1 6 0 2 b y jcs c d e f g , 6 c brand db lectro inc. d display type h character type, g graphic type , p pled e display font character 16 words, 2lines. f model serials no. g backlight type y yellow green er r special code jcs: english and japanese standard font 2.precautions in use of pled modules (1)avoid applying excessive shocks to the module or making any alteration s or modifications to it. (2)don?t make extra holes on the printed circ uit board, modify its shape or change the components of pled module. (3)don?t disassemble the pledm. (4)don?t operate it above th e absolute maximum rating. (5)don?t drop, bend or twist pledm. (6)soldering: only to the i/o terminals. (7)storage: please storage in anti-static el ectricity container and clean environment. 3.general specification item dimension unit number of characters 16 characters x 2 lines module dimension 80.0 x 36.0 x 9.7(max) mm view area 66.0 x 16.0 mm active area 50.67 x 10.36 mm dot size 0.51 x 0.60 mm dot pitch 0.54 x 0.63 mm character size 2.67 x 5.01 mm character pitch 3.20 x 5.35 mm lcd type pled , green
5 ? 19 duty 1/16 4.absolute maximum ratings item symbol min typ max unit operating temperature t op -20 25 +50 storage temperature t st -30 +70 input voltage v i -0.3 v dd v supply voltage for logic v dd -v ss -0.3 7 v supply voltage for lcd v bt- v ss -0.3 5.0 v 5.electrical characteristics item symbol condition min typ max unit supply voltage for logic v dd -v ss 4.5 5.0 5.5 v supply voltage for lcd v bt ta=25 2.0 2.5 5.0 v input high volt. v ih 0.7 v dd v dd v input low volt. v il -0.3 0.55 v output high volt. v oh 2.4 v output low volt. v ol 0.4 v supply current i dd v dd =5v 0.35 0.6 ma 6.optical characteristics item symbol condition min typ max unit
6 ? 19 (v) 80 deg view angle (h) 80 deg contrast ratio cr 100 lux 100 t rise 10 us response time t fall 10 us brightness with polarizer 40 nits 7.interface pin function pin no. symbol level description 1 v ss 0v ground 2 v dd 5.0v supply voltage for logic 3 v bt (variable) operating voltage for pled brightness adjhstment 4 rs h/l h: data, l: instruction code 5 r/w h/l h: read(mpu module) l: write(mpu module) 6 e h,h l chip enable signal 7 db0 h/l data bit 0 8 db1 h/l data bit 1 9 db2 h/l data bit 2 10 db3 h/l data bit 3 11 db4 h/l data bit 4 12 db5 h/l data bit 5 13 db6 h/l data bit 6 14 db7 h/l data bit 7 15 nc 16 nc
7 ? 19 brightness control vbt brightness(nits) power consump tion(measured with random texts) 2.5v 20(typical) 50mw 3.0v 45(typical) 63mw note:1.when random texts pattern is running,averagely ,at any instance,about 1/4 of pixels will be on. 2.if vbt is not operated within 2v and 3v,non-uniformity display may occur. 3.you have to use the saving mode by vbt 2.5v in order to make long life. 8.contour drawing & block diagram
8 ? 19 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0a 4a 0b 4b 0c 4c 0d 4d 0e 4e 0f 4f 3 12 45678910 14 12 11 13 16 15 character located ddram address ddram address mpu 80 series rs r/w e db0~db7 or 68 series controller/com driver 16x2 lcd com1~16 seg1~40 d seg driver m cl1 cl2 seg41~80 vdd,vss,vbt bias and power circuit vdd vbt vss 4.6 75.0 2.5 40.55 80.0 0.5 36.0 0.5 5.7 10.3 13.12 31.0 2.5 18.3 4.95 7.55 15.21 8.0 p2.54*15=38.1 1.8 16- 1.0pth 2 9.7max 4.9 1.6 4- 2.5 pth 4- 5.0 pad 25.2 16.0(va) 10.36(aa) 71.2 64.0(va) 50.67(aa) vss rs r/w vo db2 db0 db1 e vdd 9 7 8 6 2 4 5 3 1 db6 db4 db5 nc nc db7 13 16 15 14 11 12 10 db3 0.34 0.53 0.51 0.54 2.67 0.6 0.63 5.01 dot sizes 1 16
9 ? 19 9.function description the lcd display module is built in a lsi contro ller, the controller has two 8-bit registers, an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as displa y clear and cursor shift, and address information for display data ram (ddram) and character ge nerator (cgram). the ir can only be written from the mpu. the dr temporarily stores da ta to be written or read from ddram or cgram. when address information is written into the ir, then data is st ored into the dr from ddram or cgram. by the register selector (r s) signal, these two registers can be selected. rs r/w operation 0 0 ir write as an internal op eration (display clear, etc.) 0 1 read busy flag (db7) and address counter (db0 to db7) 1 0 write data to ddram or cg ram (dr to ddram or cgram) 1 1 read data from ddram or cg ram (ddram or cgram to dr) busy flag (bf) when the busy flag is 1, the controller lsi is in the intern al operation mode, and the next instruction will not be accepted. when rs=0 a nd r/w=1, the busy flag is output to db7. the next instruction must be written after ensuring that the busy flag is 0. address counter (ac) the address counter (ac) assigns ad dresses to both ddram and cgram display data ram (ddram) this ddram is used to store the display data represented in 8-bit character codes. its extended capacity is 80 8 bits or 80 characters. below figur e is the relationships between ddram addresses and positions on the liquid crystal display. ac (hexadecimal) high bits low bits ac6 ac5 ac4 ac3 ac2 ac1 ac0 1 0 0 1 1 1 0 example: ddram addresses 4e
10 ? 19 character generator rom (cgrom) the cgrom generate 5 8 dot or 5 10 dot character patterns from 8-bit character codes. see table 2. character generator ram (cgram) in cgram, the user can rewr ite character by program. for 5 8 dots, eight character patterns can be written, and for 5 10 dots, four character patterns can be written. write into ddram the character code at the addr esses shown as the left column of table 1. to show the character patte rns stored in cgram. display position ddram address 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 2-line by 16-character display 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
11 ? 19 relationship between cgram addresses, character codes (ddram) and character patterns table 1. f or 5 * 8 dot character patterns character codes ( ddram data ) cgram address character patterns ( cgram data ) 543210 6 75432 0 176543210 000 0 01 1 00 1 01 0 10 0 11 1 10 1 11 0 00 0 01 1 00 1 01 0 10 0 11 1 10 1 11 0 00 0 01 0 10 0 11 1 10 1 11 *** *** *** *** *** *** *** ***00000 *** *** *** *** *** *** *** ***00000 00 00 00 00 00 00 000 000 000 00 0 000 0 000 000 0 000 0 01 *** *** 111 0000 *111 0000 *000 0000 *001 h igh l o w h igh l o w h igh l ow for 5 * 10 dot character patterns character codes ( ddram data ) cgram address character patterns ( cgram data ) 7 h igh l o w 4 5 63210 h igh l o w 543210 h igh l o w 765 4 1 2 30 ***00000 00000 *** *** *** *** *** *** *** *** *** *** ******** 0000 0001 0010 0011 0100 0101 0110 0111 1000 100 1 10 10 1111 00000 0000 *000 00 00 00 000 000 0 0000 0000 0000 character pattern( 1 ) cursor pattern character pattern( 2 ) cursor pattern character pattern cursor pattern : " h igh "
12 ? 19 10.character generator rom pattern table.2 llll lllh llhl llhh lhll lhlh lhhl lhhh hlll hllh hlhl hlhh hhll hhlh hhhl upper 4 bit lower 4 bit llll lllh llhl llhh lhll lhlh lhhl lhhh hlll hllh hlhl hlhh hhll hhlh hhhl hhhh hhhh cg ram ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 )
13 ? 19 11.instruction table instruction code instruction rs r/w db7 db6 db5 db4 db3 db2 db1 db0 description execution time (fosc=270khz) clear display 0 0 0 0 0 0 0 0 0 1 write ?00h? to ddram and set ddram address to ?00h? from ac 1.52ms return home 0 0 0 0 0 0 0 0 1 set ddram address to ?00h? from ac and return cursor to its original position if shifted. the cont ents of ddram are not changed. 1.52ms entry mode set 0 0 0 0 0 0 0 1 i/d sh assign cursor moving direction and enable the shift of entire display. i/d=1:increment 0: decrement sh=1:display shift on 37 s display on/off control 0 0 0 0 0 0 1 d c b set display (d), cursor (c), and blinking of cursor (b) on/off control bit. d=1:display on c=1:cursor display on b=1:cursor blink on 37 s cursor or display shift 0 0 0 0 0 1 s/c r/l set cursor moving and display shift control bit, and the direction, without changing of ddram data. s/c=1:shift display 0:move cursor r/l=1:shift right 0:shift leftf 37 s function set 0 0 0 0 1 dl n f set interface data length (dl) dl=1:8-bit 0:4-bit set numbers of display lines(n) n=1:dual line 0:single line set display font type (f) f=1:5x10 dots 0:5x8dots 37 s set cgram address 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 37 s set ddram address 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 37 s read busy flag and address 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. bf=1:internal operation bf=0:ready for instruction 0 s write data to ram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 37 s read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 37 s ? ? don?t care
14 ? 19 12.timing characteristics 12.1 write operation ta=25 , vdd=5 .0 0.5v item symbol min typ max unit enable cycle time t cyce 500 ns enable pulse width (high level) pw eh 230 ns enable rise/fall time t er ,t ef 20 ns address set-up time (rs, r/w to e) t as 40 ns address hold time t ah 10 ns data set-up time t dsw 80 ns data hold time t h 10 ns vih1 vil1 vih1 vil1 vil1 t cyce vih1 vil1 vih1 vil1 vil1 t as t ah t ah t ef t h t dsw pw eh t er vil1 vih1 vil1 vih1 vil1 rs r/w e db0 to db7 valid data
15 ? 19 12.2 read operation ta=25 , vdd=5 .0 0.5v item symbol min typ max unit enable cycle time t cyce 500 ns enable pulse width (high level) pw eh 230 ns enable rise/fall time t er ,t ef 20 ns address set-up time (rs, r/w to e) t as 40 ns address hold time t ah 10 ns data delay time t ddr 160 ns data hold time t dhr 5 ns vih1 vil1 vih1 vil1 t cyce voh1 vol1* t as t ah t ah t ef t dhr pw eh t er vil1 vih1 vil1 vih1 vil1 rs r/w e db0 to db7 vih1 vih1 voh1 *vol1 valid data t ddr note: *vol1 is assumed to be 0.8v at 2 mhz operation.
16 ? 19 13.initializing of lcm power on rs r/w db7 db6 db5 db4 db3 db2 db1 db0 000011**** wait for more than 15 ms after v cc rises to 4.5 v wait for more than 4.1 ms 1 db4 db7 0 rs 0 r/w db6 00 db5 1 db1 db2 db3 **** db0 wait for more than 100 s db4 1 db7 r/w rs 00 db5 db6 001 db1 db3 db2 *** db0 * 1 db4 db7 0 0 rs r/w 1 00 db6 db5 db1 f* n db2 db3 * db0 0000001000 0000000001 00000001 i/d s initialization ends bf can not be checked before this instruction. function set ( interface is 8 bits long. ) function set ( interface is 8 bits long. ) bf can not be checked before this instruction. bf can not be checked before this instruction. function set ( interface is 8 bits long. ) bf can be checked after the following instructions. when bf is not checked , the waiting time between instructions is longer than execution instruction time. function set ( interface is 8 bits long. specify the number of display lines and font. ) the number of display lines and character font can not be changed after this point. 8-bit ineterface display off display clear entry mode set
17 ? 19 power on rs r/w db7 db6 db5 db4 000011 wait for more than 15 ms after v cc rises to 4.5 v wait for more than 4.1 ms wait for more than 100 s 0 db4 db7 0 0 rs r/w 1 00 db6 db5 000010 00nf** 000000 initialization ends bf can not be checked before this instruction. function set ( interface is 8 bits long. ) function set ( interface is 8 bits long. ) bf can not be checked before this instruction. bf can not be checked before this instruction. function set ( interface is 8 bits long. ) bf can be checked after the following instructions. when bf is not checked , the waiting time between instructions is longer than execution in struction time. function set ( set interface to be 4 bits long. ) interface is 8 bits in length. function set ( interface is 4 bits long. specify the number of display lines and character font. ) the number of display lines and character font can not be changed after this point. display off display clear entry mode set 4-bit ineterface 0 db6 rs r/w 00 db7 0 db4 db5 11 db6 0 rs r/w 00 db7 0 db4 db5 11 001000 000000 000001 000000 000 i/d s 1
18 ? 19 14.quality assurance screen cosmetic criteria item defect judgment criterion partition 1 spots a)clear size: d mm acceptable qty in active area d Q 0.1 disregard 0.1 19 ? 19 15.reliability content of reliability test environmental test test item content of test test condition applicable standard high temperature storage endurance test applying the high storage temperature for a long time. 70 200hrs ?? low temperature storage endurance test applying the high storage temperature for a long time. -30 200hrs ?? high temperature operation endurance test applying the electric stress (voltage & current) and the thermal stress to the element for a long time. 50 200hrs ?? low temperature operation endurance test applying the electric stress under low temperature for a long time. -20 200hrs ?? high temperature/ humidity storage endurance test applying the high temperature and high humidity storage for a long time. 70 ,90%rh 96hrs ?? high temperature/ humidity operation endurance test applying the electric stress (voltage & current) and temperature / humidity stress to the element for a long time. 50 ,90%rh 96hrs ?? temperature cycle endurance test applying the low and high temperature cycle. -20 25 50 30min 5min 30min 1 cycle -20 /50 10 cycles ?? mechanical test vibration test endurance test applying the vibration during transportation and using. 10~22hz 1.5mmp-p 22~500hz 1.5g total 0.5hrs ?? shock test constructional and mechanical endurance test applying the shock during transportation. 50g half sign wave 11 msedc 3 times of each direction ?? atmospheric pressure test endurance test applying the atmospheric pressure during transportation by air. 115mbar 40hrs ?? others static electricity test endurance test applying the electric stress to the terminal. vs=800v,rs=1.5k cs=100pf 1 time ?? ***supply voltage for logic system=5v. supply voltage for lcd system =operating voltage at 25

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